Image reading apparatus

ABSTRACT

Since a power supply circuit for a controller ( 31 ) and a power supply circuit for a buffer storage unit ( 32 ) are independently provided, the power voltage for the buffer storage unit ( 32 ) need only be reduced to obtain a corresponding reduction in the amplitude of the signal waveform of digital image data transmitted along an FFC ( 40 ), without the operation of the controller ( 31 ) being adversely affected. In addition, so long as a coil ( 47 ) is located at one position in the internal power supply circuit of a control chip ( 24 ), or the external circuit thereof near its power supply circuit, the signal waveform for the digital image data transmitted along the FFC ( 40 ) can be attenuated.

BACKGROUND OF THE INVENTION

The present invention relates to an image reading apparatus, and relatesin particular to an EMI (Electro Magnetic Interference) countermeasuretherefor.

Image reading apparatuses, such as image scanners and facsimilemachines, are well known as digital image input apparatuses that for useare now closely associated with computers. Concurrently, as thedevelopment of the computers with which they are now generally employedhas continued, the reading speeds attained by these image readingapparatuses have been increased, year after year.

As is shown in FIG. 4, for a conventional flatbed image scanner, a CCD22, an A/D converter 25 and a buffer 28 are provided for a carriage 20,and an image processing ASIC 52, which incorporates a controller 51 forgenerating control signals for the CCD 22 and the A/D converter 25, isprovided for a main substrate 41 that is fixed to a case 11. The imageprocessing ASIC 52 is connected to the CCD 22, the A/D converter 25 andthe buffer 28 by a flexible flat cable (hereinafter referred to as anFFC) several tens of centimeters in length. Since for this conventionalflatbed scanner configuration the path provided by the FFC for thetransmission of digital image data signals is very long, it is anacknowledged fact that appropriate EMI (ElectroMagnetic Interference)countermeasures are required for the FFC.

However, to reduce the EMI that accompanies the transmission of digitalimage data along the FFC, EMI countermeasures must be taken for theindividual FFC data lines by providing a resistor for each of them, andthis provision of EMI countermeasures would increase the overall unitcost.

SUMMARY OF THE INVENTION

It is, therefore, one objective of the present invention to provide animage reading apparatus for which a reduction in operating frequency canbe prevented, and for which costs are minimized for measures taken toreduce the EMI accompanying the transmission of digital image data.

In order to solve the aforesaid object, the invention is characterizedby having the following arrangement.

-   (1) An image reading apparatus comprising:

an image input unit for generating analog image data corresponding tooptical density data for a document;

an A/D converter for converting, into digital image data, analog imagedata received by the image input unit;

an image processing unit for performing image processing based on thedigital image data;

a control chip, including

-   -   a controller for controlling the image input unit and the A/D        converter, and    -   a buffer storage unit for transmitting, to the image processing        unit, the digital image data output by the A/D converter,        wherein a power supply circuit for the controller and a power        supply circuit for the buffer storage unit are independently        provided; and

a wiring member for electrically connecting the image processing unitand the control chip.

-   (2) The image reading apparatus according to (1), wherein the power    voltage for the buffer storage unit is less than the power voltage    for the controller.-   (3) The image reading apparatus according to (1) further comprising:

a waveform control member for attenuating the signal waveform of thepower supply circuit for the buffer storage unit.

-   (4) The reading apparatus according to (3), wherein the waveform    control member includes a coil.-   (5) The image reading apparatus according to (1), wherein the wiring    member is a flexible flat cable.-   (6) The image reading apparatus according to (1), wherein

the image processing unit is provided for a case,

the image input unit, the A/D converter and the control chip are mountedon a carriage movable with respect to the case.

-   (7) The image reading apparatus according to (1), wherein the wiring    member includes a power feed line for the power supply circuit for    the controller and a power feed line for the power supply circuit    for the buffer storage unit.-   (8) The image reading apparatus according to (7) further comprising    a coil provided for the power feed line for the power supply circuit    for the buffer storage unit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a scanner according to one embodimentof the present invention;

FIG. 2 is a specific cross-sectional view of the scanner according tothe embodiment of the invention;

FIG. 3 is a block diagram showing a control chip according to theembodiment of the invention; and

FIG. 4 is a specific cross-sectional view of a conventional scanner.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

With referring to the drawings, an explanation will now be given for ascanner constituting an image reading apparatus according to oneembodiment of the present invention. As shown in FIG. 2, a flatbedscanner according to the embodiment is includes a carriage 20 thatreciprocates parallel to the face of a document.

Located on the periphery of a glass document table 10, which is providedon the upper face of a box shaped case 11, is a document guide (notshown) for positioning a document on the face of the glass documenttable 10. A white reference mark (not shown) having a uniform, highlyreflective face is provided at the end of the glass document table 10.

The carriage 20 is supported by a guide rod (not shown) that is fixed tothe case 11 and that permits the carriage 20 to be moved freely. A drivebelt (which is not shown) is fixed to the carriage 20, and is rotated bya driving device (also not shown). A lamp 21, which is constituted by arod shaped fluorescent lamp, is incorporated in the carriage 20, andemits light used to illuminate a document positioned on the glassdocument table 10. An optical system 30, which serves as an image inputunit, is constituted by employing multiple mirrors and lenses, and formsan optical path extending from the document face to a CCD line sensor22.

As is shown in FIG. 1, the CCD line sensor 22 that serves as the imageinput unit is provided for a substrate 48, which is fixed to thecarriage 20. The CCD line sensor 22 accumulates charges that areconsonant with the light quantity received by all light receivingelements, and outputs the accumulated charges to an amplifier 28 inaccordance with a control signal, such as a shift pulse received from acontroller 31. A CCD having a color output can also be employed as theCCD line sensor 22, which includes multiple photo-electric conversionelements, a transfer gate, an analog shift register and a charge voltageconverter. The charges accumulated by the photo-electric conversionelements are transmitted to the analog shift register in accordance withthe shift pulse received by the transfer gate. By varying the shiftpulse interval, the time allocated for the accumulation of charges atthe photo-electric conversion elements can be changed, and the transferof the charges to the analog shift register can be performed at the sametime by all the photo-electric conversion elements. The charges sotransmitted to the analog shift register are sequentially transferred tothe charge voltage converter, which then changes the charge to avoltage. The shift pulse interval, i.e., the charge accumulation timefor the photo-electric conversion element, is controlled by a computerprogram stored in a micro-computer 44.

An A/D converter 25, which is provided for the substrate 48, samples ananalog image signal received from the CCD line sensor 22, and outputsthe obtained 256 digital image signals. For sampling the analog imagesignal, the A/D converter 25 employs a sampling pulse received from thecontroller 31.

A control chip 24, formed of a single chip, is provided for thesubstrate 48. The control chip 24 constitutes an integrated circuit thatincludes the controller 31 and an output buffer 32 as a buffer storageunit. The control chip 24 receives two types of power from an imageprocessing ASIC 45 along power feed lines 35 and 36. As shown in FIG. 3,the controller 31 and the output buffer 32 include independent powersupply circuits, while two independent power terminals, i.e., the powerterminal for the controller 31 and the power terminal for the outputbuffer 32 (neither of which is shown), are provided for the control chip24. The power feed lines 35 and 36 are connected to these two powerterminals. The power voltage for the controller 31 is 5 V, and the powerfor the output buffer 32 voltage is 3.3 V. Since the power voltage forthe output buffer 32 is lower than the power voltage for the controller31, the amplitude of an image digital signal transmitted by the outputbuffer 32 to the image processing ASIC 45 can be reduced, and the EMIproduced by this signal can be suppressed. Furthermore, since the powervoltage for the output buffer 32 can be lowered without reducing thepower voltage for the controller 31, an adequate power voltage forcontrolling the CCD 22 and the A/D converter 25 is ensured, while theEMI produced by the image digital signal can be suppressed.

In this embodiment, two types of power are supplied from outside of thecontrol chip 24. However, a single type of power may be supplied fromoutside the control chip 24, and the internal regulator of the controlchip 24 may be employed to reduce the power voltage for the outputbuffer 32 so that it is lower than the power voltage at the controller31.

The controller 31 generates a secondary clock pulse of 96 MHz, andemploys the secondary clock pulse to generate a shift pulse and a resetpulse that it outputs to the CCD line sensor 22 and the A/D converter25. For the generation of the secondary clock pulse, a PLL circuit inthe controller 31 is employed to multiply by 16 the primary clock pulsereceived by the controller 31. It should be noted that the frequency ofthe secondary clock pulse only need to be determined in accordance withthe functions of the CCD line sensor 22 and the A/D converter 25. As thefrequency of the secondary clock pulse goes higher, a control signalhaving a narrower pulse width is generated, and as the pulse width ofthe control signal becomes narrower, the CCD line sensor 22 and the A/Dconverter can be operated at a higher speed. These signals generated bythe controller 31 are transmitted to the CCD line sensor 22 along fivecontrol lines 23, and are transmitted to the A/D converter 25 along fourcontrol lines 26. As described above, since the controller 31 multipliesthe frequency of the clock pulse, the CCD line sensor 22 and the A/Dconverter 25 can be operated at high speeds.

Since the transmission paths along data lines 27 and 29 in FIG. 2 areshorter than data line 33 for an FFC 40, less noise may enter and lesssignal waveform deterioration occurs along the data lines 27 and 29 thanalong the data line 33. Therefore, an analog image signal output by theCCD line sensor 22 is precisely converted into a digital image signal.Further, since the transmission paths along the control lines 23 and 26are shorter than a control line 34 for the FFC 40, during thetransmission of a control signal having a small pulse width and havingthe sharp leading and trailing edges of the pulse, EMI noise seldomoccurs along the control lines 23 and 26 as compared with the controlline 34.

The output buffer 32 is constituted by multiple flip-flop circuitslocated along the data lines 33, and the output buffer 32 enhances thedriving capacity of a digital electric signal output by the A/Dconverter 25. In addition, since the digital image data obtained throughthe sampling performed by the A/D converter 25 are temporarily stored inthe output buffer 32, and since the timing for transmitting the signalto the data lines 33 of the FFC is adjusted, the peak value of the EMInoise is reduced.

As is shown in FIG. 1, for the output buffer 32 a coil 47 is provided asa waveform control member along a power feed line 36. The coil 47 may belocated either inside or outside the control chip 24; however, it ispreferable that the coil 47 be located as near as possible to the outputbuffer 32. It should be noted that instead of the coil 47, a resistormaybe employed as the waveform control unit. Since the waveform controlunit, such as the coil 47, is provided for the power supply system ofthe output buffer 32, the waveform of the digital image signaltransmitted by the output buffer 32, through the FFC 40, to the imageprocessing ASIC 45 can be attenuated. Since the power supply system forthe output buffer 32 and the power supply system for the controller 31are independent of each other, even when the waveform control member,such as the coil 47, is provided for the power supply system for theoutput buffer 32, the waveform of the control signal that is output bythe controller 31 to the CCD 22 and the A/D converter 25 is notattenuated. Therefore, the controller 31 can employ a control signalhaving a high frequency to drive the CCD 22 and the A/D converter 25 ata high speed.

When one type of power is supplied from outside the control chip 24, andthe internal transformer in the control chip 24 is employed to reducethe power voltage of the output buffer 32 so that it is lower than thepower voltage at the controller 31, the coil 47 must be provided at apower supply circuit that is independent of the power supply circuit ofthe controller 31, and that has a lower power voltage than that of thecontroller 31.

As shown in FIG. 1, the eight-bit width data line 33, the control line34 and the power feed lines 35, 36, 37, 38 and 39 are provided for theFFC 40. The digital image signal, of eight bits, is transmitted from theA/D converter 25 to the image processing ASIC 45 along the data line 33.When the CCD line sensor 22 outputs color image data, image signals forR (Red), G (Green) and B (Blue) are transmitted to the image processingASIC 45 in a time sharing manner. The primary clock pulse is transmittedby the image processing ASIC 45 to the controller 31 along the controlline 34. The two ends of the FFC 40 are secured to a connector (notshown) provided for the substrate 48 and a connector (also not shown)provided for a main substrate 41. The length of the FFC 40 is sufficientfor the carriage 20 to reciprocate, within a distance of about 30 cm,parallel to the document glass table 10.

As is shown in FIG. 2, the main substrate 41 is fixed to the case 11.The image processing ASIC 45, an interface 43 and the micro-computer 44,which are interconnected by a bus 42, are mounted on the main substrate41.

The image processing ASIC 45, which serves as an image processing unit,compares white reference data, which is obtained by scanning a whitereference before the reading is started, with black reference data thathave been stored in advance, corrects variances in the sensitivity ofeach element in the CCD line sensor 22 and variances in the quantity oflight emitted by the lamp 21 in the main scanning direction, andperforms various other processes, such as gamma correction and colorcorrection. The image processing ASIC 45 includes a clock generator 46,which generates the primary clock pulse of 6 MHz that it thereaftertransmits to the controller 31.

The interface 43 is used to connect a host computer (not shown) to thescanner. The micro-computer 44 includes a CPU, a RAM and a ROM, andprovides overall control for the entire scanner, including the imageprocessing ASIC 45, the interface 43 and the control chip 24.

The configuration of the scanner according to the embodiment of theinvention has been explained. The operation of this scanner will now bedescribed. Upon receiving a read start command from the host computer44, the micro-computer 44 executes a predetermined program employed toactivate the scanner in the following manner.

Under the control of the micro-computer 44, the lamp 21 is turned on andthe white reference data is obtained. Then, the carriage 20 is moved toa position corresponding to a reading origin by a driving device (notshown). The optical system 30 is used to form an image on the CCD linesensor 22 of a document positioned on the glass document table 10. Thecontroller 31 generates the secondary clock pulse of 96 MHz, based onthe primary clock pulse of 6 MHz that is output by the image processingASIC 45, employs the secondary clock pulse to generate control signals,such as a shift pulse, and controls the CCD line sensor 22 based onthese control signals. As the frequency of the control signal, such asthe shift pulse, is high and the pulse width is narrow, the CCD linesensor 22 can be operated at a high speed.

Synchronized with the shift pulse, a charge is obtained from the CCDline sensor 22 and is transmitted as an analog image signal to theamplifier 28. For each line, the CCD line sensor 22 transmits a chargeto the shift register, and each time a charge has been so transmitted,the driving device moves the carriage 20 to the next reading line. Basedon a sampling pulse received from the controller 31, the analog imagesignal amplified by the amplifier 28 is sampled by the A/D converter 25and is converted into a digital image signal of eight bits. As thesampling pulse frequency is high and the pulse width is narrow, only ashort cycle is required to sample the analog image signal output by theCCD line sensor 22. Subsequently, the digital image signal istemporarily stored in the output buffer 32, and is then transmitted tothe data lines 33 at transfer timings that differ for the individualdata lines. Finally, the image processing ASIC 45 performs shadingcorrection or gamma correction for the received digital image data andtransmits the obtained data, through the interface 43, to the hostcomputer.

According to the scanner of this embodiment, since as is shown in FIG. 3the power supply circuit for the controller 31 and the power supplycircuit for the output buffer 32 are independently provided, the powervoltage for the output buffer 32 need only be reduced to obtain acorresponding reduction in the amplitude of the signal waveform of thedigital image data transmitted along the FFC 40, without the operationof the controller 31 being adversely affected. In addition, so long asthe coil 47 is located at one position in the internal power supplycircuit of the control chip 24, or the external circuit thereof near itspower supply circuit, the signal waveform for the digital image datatransmitted along the FFC 40 can be attenuated. Therefore, a highoperating frequency can be maintained, and the costs incurred by thereduction of the EMI that accompanies the transmission of digital imagedata can be minimized.

1. An image reading apparatus comprising: an image input unit forgenerating analog image data corresponding to optical density data for adocument; an A/D converter for converting, into digital image data,analog image data received by the image input unit; an image processingunit for performing image processing based on the digital image data; acontrol chip, including a controller for controlling the image inputunit and the A/D converter, and a buffer storage unit for transmitting,to the image processing unit, the digital image data output by the A/Dconverter, wherein a power supply circuit for the controller and a powersupply circuit for the buffer storage unit are independently provided;and a wiring member for electrically connecting the image processingunit and the control chip.
 2. The image reading apparatus according toclaim 1, wherein the power voltage for the buffer storage unit is lessthan the power voltage for the controller.
 3. The image readingapparatus according to claim 1 further comprising: a waveform controlmember for attenuating the signal waveform of the power supply circuitfor the buffer storage unit.
 4. The reading apparatus according to claim3, wherein the waveform control member is a coil.
 5. The image readingapparatus according to claim 1, wherein the wiring member is a flexibleflat cable.
 6. The image reading apparatus according to claim 1, whereinthe image processing unit is provided for a case, the image input unit,the A/D converter and the control chip are mounted on a carriage movablewith respect to the case.
 7. The image reading apparatus according toclaim 1, wherein the wiring member includes a power feed line for thepower supply circuit for the controller and a power feed line for thepower supply circuit for the buffer storage unit.
 8. The image readingapparatus according to claim 7 further comprising a coil provided forthe power feed line for the power supply circuit for the buffer storageunit.